1. Field of the Invention
This invention relates to the field of superscalar microprocessors and, more particularly, to mask generation within superscalar microprocessors.
2. Description of the Relevant Art
Masking is a useful function in many types of logic circuits. As used herein, a "mask" is a pattern of binary ones and zeros which is used to set or clear particular bits of a value while leaving other bits of the value unchanged. Each bit of the mask corresponds to a bit in the value. When the mask and the value are logically ANDed or ORed together, each bit of the mask is ANDed or ORed with the corresponding bit in the value. If bits are intended to be cleared using the mask, then the mask is logically ANDed with the value. Bits of the mask corresponding to bits in the value that are to be cleared are binary zeros. The bits of the mask corresponding to bits of the value that are to remain unchanged are binary ones. Conversely, if bits are intended to be set using the mask then the mask is logically ORed with the value. For this mask, the bits of the mask corresponding to bits in the value that are to be set are binary ones. Bits of the mask that are to be left unchanged are binary zeros.
An exemplary function that masking may perform is extraction of a value from a field of values. The value of interest may lie between two bit locations in the field. A mask used for the extraction contains a bit for each bit in the field of values. Bits between the two bit locations of the mask corresponding to the value of interest are set, while other bit locations are cleared. By ANDing this mask with the field of values, all other values in the field would be set to zero. The result could then be shifted to leave the value of interest, and no extraneous bits in the result would be set.
The same mask may also be used with a second mask to insert the value into the field. The second mask is the logical inversion of the first mask: each bit position of the second mask is the logical inverse of the respective bit position in the original mask. The second mask is ANDed with the field to clear the bits of the field in which the value is to be stored. Then, the value is shifted such that its bits align with the cleared bit locations. The shifted value is logically ANDed with the mask to remove any extraneous bits that may be set, and the result may then be ORed with the field. The bits of the value are ORed with zeros and so the value is stored into the field, and other bits of the field are similarly ORed with zeros from the shifted value. Many other uses for masks are well known in the art.
The pattern of bits in the mask are often said to be "ordered". As used herein with respect to masks, the term "ordered" means that the bit location within the mask associated with a particular bit value denotes the interpretation of that bit value. For example, the bits that form a mask are ordered. Each bit of the mask is numbered, starting at zero and ending with the number of bits within the mask minus one. A bit which is associated with a bit location numbered higher than the bit location associated with a second bit is said to be a higher order bit than the second bit. Conversely, a bit which is associated with a bit location numbered lower than the bit location associated with a second bit is said to be a lower order bit than the second bit. Additionally, a group of bits may be referred to as high order bits or low order bits. High order bits are a group of bits which are associated with the highest order bit locations that a value includes, and low order bits are a group of bits which are associated with the lowest order bit locations that a value includes. As an example, the high order bits of a mask as typically displayed are the bits to the left, and the low order bits are the bits to the right. This high and low order bit designation will be useful in the discussion to follow.
Although masks may be any pattern of binary ones and zeros, a particularly interesting mask for many applications is one which is a set of contiguous binary ones with a set of contiguous binary zeros in higher order or lower order bits (or both). The inverse of this mask (a set of contiguous binary zeros with a set of contiguous binary ones in higher order or lower order bits, or both) is also a particularly interesting mask. These masks may be used for extracting and inserting values (as described above), among other uses. Exemplary eight bit masks of this type are: 00111000, 11110000, 00001111, and 11000011. Masks of this type in which the contiguous zeros are in low order bits and the contiguous ones are in high order bits (or vice versa) may be characterized by noting the bit position at which the high order bits and low order bits meet. This number could then be used to generate the mask, by filling bit locations of higher order than the indicated bit location with binary ones and filling bit locations of lower order than the indicated bit location with binary zeros. Since the number may be stored in fewer bits than the mask itself, storage space may be saved by using the number to indicate the mask instead of the mask bit itself. The longer the mask (i.e. the larger the number of bits in the mask), the more advantageous this space saving becomes.
Unfortunately, generating a large mask from such a value typically requires a large number of gates. Conventionally, such a mask generation may have been performed by determining for each bit whether or not the number mentioned above indicates that the bit is a high order bit. Therefore, the logic for generating each bit of the mask is the logical OR of numerous AND gates. Each AND gate identifies a particular number (i.e. the AND gate decodes that number). The AND gates included for a particular bit decode each number between that bit location and bit location zero. As an example, bit three of such a mask is a high order bit (and should be set to a binary one) if the number indicates that the boundary between low and high order bits is bit two, bit one, or bit zero. In this scheme, the lowest order bit of an N-bit number is bit zero and the highest order bit is bit N-1. In addition to the large number of logic gates (and hence the amount of silicon area used to implement the mask generation on an integrated circuit), the number of cascaded levels of logic necessary to generate the mask having a large number of bits is prohibitive to high frequency integrated circuits.
One type of high frequency integrated circuit which uses masking is a superscalar microprocessor. Within a superscalar microprocessor, many different values may require masking. Additionally, the values that require masking are often quite wide. For example, values that are 32 bits or 64 bits in width are common in modern day superscalar microprocessors. Therefore, a mask generator utilizing a low number of cascaded logic levels and a low number of logic gates is desired.